1. Field of the Invention
The present invention relates to a test device and test method, and more particularly, to a test device and test method by connecting multiple pads in scribe lines to test multiple pads of a chip using single probe.
2. Description of the Prior Art
Nowadays the semiconductor process is mature and well developed to create integrated circuits (ICs) that widely used in electrical and electronic devices, where the ICs play the core computing element for versatile application and functional control. As the semiconductor process advances intricately, adaptive testing equipment and relative testing methods are developed for testing the functionality and quality of the ICs. For example, a pad test for the ICs aims at testing connectivity of wire-bonding or gold bump, which avoids the ICs with bad connectivity from packaging to achieve defective elimination and quality control in the market.
FIG. 1 is a schematic diagram of a wafer 1. The wafer 1 includes a plurality of chips (or die) 10, where scribe lines 12 are formed around the chips 10. The pad test is performed to the wafer 1 once it is made. Afterwards, packaging and dicing processes are performed to the wafer 1 to encapsulate the chip 10, and then chips 10 are separated by dicing along the scribe lines 12 to remove the scribe lines 12. Finally, the chips 10 are ready for shipment.
However, as the semiconductor process advances and becomes more intricate, the number of pads of the chip increases. In order to increase the number of the chips manufactured in the wafer under the same area for yield rate improvement, the pad size becomes smaller and the pads of the chip are distributed denser under the same area. Further, the number of probes of the conventional test device (e.g., probe card) must be equal to the number of all pads of one chip, so the number of probes is correspondingly increased and the probes are distributed denser at the same time, which makes the circuit design of the test device more complicated and leads to higher productive effort for the test device. Usually, the higher density of the probes (e.g., the pitch between two probes is too close) leads to higher cost, worse reliability, and short lifetime of the test device.
Therefore, how to design a test device for the pad test to solve the issues above mentioned and improve the reliability has become a challenge in the industry.